View AD8671_7157450.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

ultralow noise amplifier at lower power data sheet ada4075-2 rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2008C2011 analog devices, inc. all rights reserved. features ultralow noise: 2.8 nv/hz at 1 khz typical ultralow distortion: 0.0002% typical low supply current: 1.8 ma per amplifier typical offset voltage: 1 mv maximum bandwidth: 6.5 mhz typical slew rate: 12 v/s typical dual-supply operation: 4.5 v to 18 v unity-gain stable extended industrial temperature range 8-lead soic and 2 mm 2 mm lfcsp packages applications precision instrumentation professional audio active filters low noise amplifier front end integrators pin configurations outa 1 ?ina 2 +ina 3 v? 4 v+ 8 outb 7 ?inb 6 +inb 5 ada4075-2 top view (not to scale) 0 7642-001 figure 1. 8-lead soic 07642-002 top view (not to scale) ada4075-2 3 +ina 4 v? 1 outa 2 ?ina 6?inb 5+inb 8v+ 7outb figure 2. 8-lead, 2 mm 2 mm lfcsp general description the ada4075-2 is a dual, high performance, low noise operational amplifier combining excellent dc and ac characteristics on the analog devices, inc., i polar? process. the i polar process is an advanced bipolar technology implementing vertical junction isolation with lateral trench isolation. this allows for low noise performance amplifiers in smaller die size at faster speed and lower power. its high slew rate, low distortion, and ultralow noise make the ada4075-2 ideal for high fidelity audio and high performance instrumentation applications. it is also especially useful for lower power demands, small enclosures, and high density applications. the ada4075-2 is specified for the ?40c to +125c temperature range and is available in a standard soic package and a 2 mm 2 mm lfcsp package. table 1. low noise precision op amps supply 44 v 36 v 12 v to 16 v 5 v single op27 AD8671 ad8665 ad8605 ad8675 op162 ad8655 ad8597 ad8691 ada4004-1 ad797 dual op275 ad8672 ad8666 ad8606 ad8676 op262 ad8656 ad8599 ad8692 ada4004-2 quad ad8674 ad8668 ad8608 ada4004-4 op462 ad8694
ada4075-2 data sheet rev. b | page 2 of 24 table of contents features .............................................................................................. 1 ? applications....................................................................................... 1 ? pin configurations ........................................................................... 1 ? general description ......................................................................... 1 ? revision history ............................................................................... 2 ? specifications..................................................................................... 3 ? absolute maximum ratings............................................................ 5 ? thermal resistance ...................................................................... 5 ? power sequencing ........................................................................ 5 ? esd caution.................................................................................. 5 ? typical performance characteristics ............................................. 6 ? applications information .............................................................. 16 ? input protection ......................................................................... 16 ? total harmonic distortion ....................................................... 16 ? phase reversal ............................................................................ 16 ? dac output filter...................................................................... 17 ? balanced line driver ................................................................. 18 ? balanced line receiver.............................................................. 19 ? low noise parametric equalizer.............................................. 20 ? schematic......................................................................................... 21 ? outline dimensions ....................................................................... 22 ? ordering guide .......................................................................... 22 ? revision history 12 /11rev. a to rev. b changes to features section............................................................ 1 8/09rev. 0 to rev. a added 8-lead lfcsp_wd ...............................................universal changes to table 1............................................................................ 1 changes to table 2............................................................................ 3 changes to table 3............................................................................ 4 changes to table 4 and table 5....................................................... 5 changes to figure 3, figure 5, figure 6, and figure 8 ................. 6 added figure 4 and figure 7; renumbered sequentially ........... 6 added figure 9 and figure 12......................................................... 7 changes to figure 10, figure 11, figure 13, and figure 14......... 7 changes to figure 16, figure 17, figure 19, and figure 20......... 8 changes to figure 22 and figure 25............................................... 9 changes to figure 36...................................................................... 11 changes to figure 54...................................................................... 14 changes to and moved figure 57 and figure 60 to ................... 15 changes to figure 59 and figure 62............................................. 15 changes to input protection section and phase reversal section .............................................................................. 16 changes to dac output filter section ....................................... 17 changes to figure 67...................................................................... 18 updated outline dimensions ....................................................... 22 changes to ordering guide .......................................................... 22 10/08revision 0: initial version
data sheet ada4075-2 rev. b | page 3 of 24 specifications v sy = 15 v, v cm = 0 v, t a = 25c, soic package, unless otherwise noted. table 2. parameter symbol conditions min typ max unit input characteristics offset voltage v os 0.2 1 mv ?40c t a +125c 1.2 mv input bias current i b 30 100 na ?40c t a +125c 150 na input offset current i os 5 50 na ?40c t a +125c 75 na input voltage range ?40c t a +125c ?12.5 +12.5 v common-mode rejection ratio cmrr v cm = ?12.5 v to +12.5 v 110 118 db ?40c t a +125c 106 db large signal voltage gain a vo r l = 2 k, v o = ?11 v to +11 v 114 117 db ?40c t a +125c 108 db r l = 600 , v o = ?10 v to +10 v 112 117 db ?40c t a +125c 106 db offset voltage drift ?v os /?t ?40c t a +125c 0.3 v/c input resistance, differential mode r indm 1.5 m input resistance, common mode r incm 500 m input capacitance, differential mode c indm 2.4 pf input capacitance, common mode c incm 2.1 pf output characteristics output voltage high v oh r l = 2 k to gnd 12.8 13 v ?40c t a +125c 12.5 v r l = 600 to gnd 12.4 12.8 v ?40c t a +125c 12 v v sy = 18 v, r l = 600 to gnd 15 15.8 v ?40c t a +125c 14 v output voltage low v ol r l = 2 k to gnd ?14 ?13.6 v ?40c t a +125c ?13 v r l = 600 to gnd ?13.6 ?13 v ?40c t a +125c ?12.5 v v sy = 18 v, r l = 600 to gnd ?16.6 ?16 v ?40c t a +125c ?15 v short-circuit current i sc 40 ma closed-loop output impedance z out f = 1 khz, a v = 1 0.1 power supply power supply rejection ratio psrr v sy = 4.5 v to 18 v 106 110 db ?40c t a +125c 100 db supply current per amplifier i sy v sy = 4.5 v to 18 v, i o = 0 ma 1.8 2.25 ma ?40c t a +125c 3.35 ma dynamic performance slew rate sr r l = 2 k, a v = 1 12 v/s settling time t s to 0.01%, v in = 10 v step, r l = 1 k 3 s gain bandwidth product gbp r l = 1 m, c l = 35 pf, a v = 1 6.5 mhz phase margin m r l = 1 m, c l = 35 pf, a v = 1 60 degrees thd + noise total harmonic distortion and noise thd + n r l = 2 k, a v = 1, v in = 3 v rms, f = 1 khz 0.0002 % noise performance voltage noise e n p-p f = 0.1 hz to 10 hz 60 nv p-p voltage noise density e n f = 1 khz 2.8 nv/hz current noise density i n f = 1 khz 1.2 pa/hz
ada4075-2 data sheet rev. b | page 4 of 24 v sy = 15 v, v cm = 0 v, t a = 25c, lfcsp package, unless otherwise noted. table 3. parameter symbol conditions min typ max unit input characteristics offset voltage v os 0.3 1 mv ?40c t a +125c 1.5 mv input bias current i b 30 100 na ?40c t a +125c 150 na input offset current i os 5 50 na ?40c t a +125c 75 na input voltage range ?40c t a +125c ?12.5 +12.5 v common-mode rejection ratio cmrr v cm = ?12.5 v to +12.5 v 110 116 db ?40c t a +125c 106 db large signal voltage gain a vo r l = 2 k, v o = ?11 v to +11 v 110 117 db ?40c t a +125c 102 db r l = 600 , v o = ?10 v to +10 v 108 117 db ?40c t a +125c 100 db offset voltage drift ?v os /?t ?40c t a +125c 3 v/c input resistance, differential mode r indm 1.5 m input resistance, common mode r incm 500 m input capacitance, differential mode c indm 2.4 pf input capacitance, common mode c incm 2.1 pf output characteristics output voltage high v oh r l = 2 k to gnd 12.8 13 v ?40c t a +125c 12.5 v r l = 600 to gnd 12.4 12.8 v ?40c t a +125c 12 v v sy = 18 v, r l = 600 to gnd 15 15.8 v ?40c t a +125c 14 v output voltage low v ol r l = 2 k to gnd ?14 ?13.6 v ?40c t a +125c ?13 v r l = 600 to gnd ?13.6 ?13 v ?40c t a +125c ?12.5 v v sy = 18 v, r l = 600 to gnd ?16.6 ?16 v ?40c t a +125c ?15 v short-circuit current i sc 40 ma closed-loop output impedance z out f = 1 khz, a v = 1 0.1 power supply power supply rejection ratio psrr v sy = 4.5 v to 18 v 100 104 db ?40c t a +125c 95 db supply current per amplifier i sy v sy = 4.5 v to 18 v, i o = 0 ma 1.8 2.25 ma ?40c t a +125c 3.35 ma dynamic performance slew rate sr r l = 2 k, a v = 1 12 v/s settling time t s to 0.01%, v in = 10 v step, r l = 1 k 3 s gain bandwidth product gbp r l = 1 m, c l = 35 pf, a v = 1 6.5 mhz phase margin m r l = 1 m, c l = 35 pf, a v = 1 60 degrees thd + noise total harmonic distortion and noise thd + n r l = 2 k, a v = 1, v in = 3 v rms, f = 1 khz 0.0002 % noise performance voltage noise e n p-p f = 0.1 hz to 10 hz 60 nv p-p voltage noise density e n f = 1 khz 2.8 nv/hz current noise density i n f = 1 khz 1.2 pa/hz
data sheet ada4075-2 rev. b | page 5 of 24 absolute maximum ratings thermal resistance table 4. parameter rating supply voltage 20 v input voltage v sy input current 1 10 ma differential input voltage 1.2 v output short-circuit duration to gnd indefinite storage temperature range ?65c to +150c operating temperature range ?40c to +125c junction temperature range ?65c to +150c lead temperature (soldering, 60 sec) 300c ja is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. this was measured using a standard 4-layer board. table 5. thermal resistance package type ja jc unit 8-lead soic 158 43 c/w 8-lead lfcsp 115 40 c/w power sequencing the op amp supplies must be established simultaneously with, or before, any input signals that are applied. if this is not possible, limit the input current to 10 ma. 1 the input pins have clamp diodes to the power supply pins. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution
ada4075-2 data sheet rev. b | page 6 of 24 typical performance characteristics t a = 25c, unless otherwise noted. 0 50 100 150 200 250 ?1.0 ?0.5 0 0.5 1.0 v sy = 15v v cm = 0v based on 600 op amps soic package 07642-003 v os (mv) number of amplifiers figure 3. input offset voltage distribution 0 20 40 60 80 100 ?1.0 ?0.5 0 0.5 1.0 v sy = 15v v cm = 0v based on 300 op amps lfcsp package 07642-040 v os (mv) number of amplifiers figure 4. input offset voltage distribution 0 10 20 30 40 50 60 70 ?2.0 ?1.6 ?1.2 ?0.8 ?0.4 0 0.4 0.8 1.2 1.6 2.0 v sy = 15v ?40c t a +125c based on 200 op amps soic package 07642-004 tcv os ( v/c) number of amplifiers figure 5. input offset voltage drift distribution 0 50 100 150 200 250 ?1.0 ?0.5 0 0.5 1.0 v sy = 5v v cm = 0v based on 600 op amps soic package 07642-006 v os (mv) number of amplifiers figure 6. input offset voltage distribution 0 20 40 60 80 100 ?1.0 ?0.5 0 0.5 1.0 v sy = 5v v cm = 0v based on 300 op amps lfcsp package 07642-042 v os (mv) number of amplifiers figure 7. input offset voltage distribution 0 10 20 30 40 50 60 80 70 ?2.0 ?1.6 ?1.2 ?0.8 ?0.4 0 0.4 0.8 1.2 1.6 2.0 07642-007 tcv os ( v/c) v sy = 5v ?40c t a +125c based on 200 op amps soic package number of amplifiers figure 8. input offset voltage drift distribution
data sheet ada4075-2 rev. b | page 7 of 24 40 35 30 25 20 15 10 5 0 01 23456 78 tcv os (v/c) number of amplifiers 07642-043 v sy = 15v v cm = 0v based on 300 op amps lfcsp package figure 9. input offset voltage drift distribution ?300 ?200 ?100 0 100 200 300 ?15 ?10 ?5 0 5 10 15 v sy = 15v based on 60 op amps 07642-005 v cm (v) v os ( v) figure 10. input offset voltage vs. common-mode voltage 07642-009 temperature (c) i b (na) 0 20 40 60 80 ?50 ?25 0 25 50 75 100 125 v sy = 15v figure 11. input bias current vs. temperature 40 35 30 25 20 15 10 5 0 012345678 tcv os (v/c) number of amplifiers 07642-052 v sy = 5v v cm = 0v based on 300 op amps lfcsp package figure 12. input offset voltage drift distribution ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 5 ?300 ?200 ?100 0 100 200 300 07642-008 v cm (v) v os ( v) v sy = 5v based on 60 op amps figure 13. input offset voltage vs. common-mode voltage 07642-012 temperature (c) i b (na) 0 20 40 60 100 80 ?50 ?25 0 25 50 75 100 125 v sy = 5v figure 14. input bias current vs. temperature
ada4075-2 data sheet rev. b | page 8 of 24 0 10 20 30 40 50 60 ?15 ?10 ?5 0 5 10 15 07642-047 v cm (v) i b (na) v sy = 15v figure 15. input bias current vs. input common-mode voltage 07642-010 load current (ma) output voltage to supply rail (v) 0.1 1 10 0.001 0.01 0.1 1 10 100 v+ ? v oh v ol ? v? v sy = 15v figure 16. output voltage to supply rail vs. load current 07642-011 temperature (c) output voltage to supply rail (v) 0 0.5 1.0 1.5 2.0 2.5 ?50 ?25 0 25 50 75 100 125 v ol ? v? v+ ? v oh v sy = 15v r l = 2k ? figure 17. output voltage to supply rail vs. temperature ?4?3?2?101234 0 10 20 30 40 50 60 07642-049 v cm (v) i b (na) v sy = 5v figure 18. input bias current vs. input common-mode voltage 07642-013 load current (ma) output voltage to supply rail (v) 0.1 1 10 0.001 0.01 0.1 1 10 100 v+ ? v oh v sy = 5v v ol ? v? figure 19. output voltage to supply rail vs. load current 07642-014 temperature (c) output voltage to supply rail (v) 0 0.5 1.0 1.5 2.0 ?50 ?25 0 25 50 75 100 125 v+ ? v oh v ol ? v? v sy = 5v r l = 2k ? figure 20. output voltage to supply rail vs. temperature
data sheet ada4075-2 rev. b | page 9 of 24 ?100 ?80 ?60 ?40 ?20 0 20 40 60 80 100 120 140 ?100 ?80 ?60 ?40 ?20 0 20 40 60 80 100 120 140 phase (degrees) gain phase 1k 10k 100k 1m 10m 100m 07642-015 frequency (hz) gain (db) v sy = 15v figure 21. open-loop gain and phase vs. frequency 07642-117 50 ?20 ?10 0 10 20 30 40 10 100 1k 10k 100k 1m 10m 100m gain (db) frequency (hz) a v = +100 v sy = 15v a v = +10 a v = +1 figure 22. closed-loop gain vs. frequency a v = +1 a v = +10 a v = +100 10 100 1k 10k 100k 1m 10m 07642-017 frequency (hz) z out ( ? ) v sy = 15v 0.001 0.01 0.1 1 10 100 1k figure 23. output im pedance vs. frequency 0 20 40 60 80 100 120 140 ?80 ?60 ?40 ?20 ?80 ?100 ?100 ?60 ?40 ?20 0 20 40 60 80 100 120 140 phase (degrees) gain phase 1k 10k 100k 1m 10m 100m 07642-018 frequency (hz) gain (db) v sy = 5v figure 24. open-loop gain and phase vs. frequency 07642-120 50 ?20 ?10 0 10 20 30 40 10 100 1k 10k 100k 1m 10m 100m gain (db) frequency (hz) a v = +100 v sy = 5v a v = +10 a v = +1 figure 25. closed-loop gain vs. frequency 10 100 1k 10k 100k 1m 10m 07642-020 frequency (hz) z out ( ? ) a v = +1 a v = +10 a v = +100 v sy = 5v 0.001 0.01 0.1 1 10 100 1k figure 26. output im pedance vs. frequency
ada4075-2 data sheet rev. b | page 10 of 24 0 20 40 60 80 100 120 140 100 1k 10k 100k 1m 10m v sy = 15v 07642-021 frequency (hz) cmrr (db) figure 27. cmrr vs. frequency ?20 0 20 40 60 80 100 120 10 100 1k 10k 100k 1m 10m 100m psrr+ psrr? 0 7642-022 frequency (hz) psrr (db) v sy = 15v figure 28. psrr vs. frequency 0 5 10 15 20 25 30 35 40 10 100 1000 07642-023 capacitance (pf) overshoot (%) v sy = 15v a v = +1 r l = 2k ? figure 29. small signal overshoot vs. load capacitance 0 20 40 60 80 100 120 140 100 1k 10k 100k 1m 10m 07642-024 frequency (hz) cmrr (db) v sy = 5v figure 30. cmrr vs. frequency ?20 0 20 40 60 80 100 120 10 100 1k 10k 100k 1m 10m 100m 07642-025 frequency (hz) psrr (db) psrr+ psrr? v sy = 5v figure 31. psrr vs. frequency 0 5 10 15 20 25 30 35 40 10 100 1000 07642-026 capacitance (pf) overshoot (%) v sy = 5v a v = +1 r l = 2k ? figure 32. small signal overshoot vs. load capacitance
data sheet ada4075-2 rev. b | page 11 of 24 v sy = 15v v in = 20v p-p a v = +1 r l = 2k ? c l = 100pf 07642-027 time (4s/div) voltage (5v/div) 0v figure 33. large signal transient response v sy = 15v v in = 100mv p-p a v = +1 r l = 2k ? c l = 100pf 07642-028 time (10s/div) voltage (20mv/div) 0v figure 34. small signal transient response 0 2 4 ?20 ?15 ?10 ?5 0 v sy = 15v input output 07642-029 time (1s/div) input voltage (v) output voltage (v) figure 35. negative overload recovery v sy = 5v v in = 7v p-p a v = +1 r l = 2k ? c l = 100pf 07642-030 time (4s/div) voltage (2v/div) 0v figure 36. large signal transient response v sy = 5v v in = 100mv p-p a v = +1 r l = 2k ? c l = 100pf 07642-031 time (10s/div) voltage (20mv/div) 0v figure 37. small signal transient response ?8 ?6 ?4 ?2 0 0 2 4 v sy = 5v input output 07642-032 time (1s/div) input voltage (v) output voltage (v) figure 38. negative overload recovery
ada4075-2 data sheet rev. b | page 12 of 24 ?2 0 2 4 v sy = 15v input output 07642-033 time (1s/div) input voltage (v) output voltage (v) ?10 ?5 0 5 10 15 figure 39. positive overload recovery 07642-061 input voltage (5v/div) time (2 s/div) output v sy = 15v ?10mv +10mv 0v error band figure 40. positive settling time to 0.01% 0 7642-064 input output v sy = 15v ?10mv +10mv 0v voltage (5v/div) time (2 s/div) error band figure 41. negative settling time to 0.01% ?2 0 2 4 v sy = 5v input output 07642-034 time (1s/div) input voltage (v) output voltage (v) ?4 ?2 0 2 4 figure 42. positive overload recovery 07642-062 input output v sy = 5v ?6mv +6mv 0v voltage (5v/div) time (2 s/div) error band figure 43. positive settling time to 0.01% 07642-063 input output v sy = 5v ?6mv +6mv 0v voltage (5v/div) time (2 s/div) error band figure 44. negative settling time to 0.01%
data sheet ada4075-2 rev. b | page 13 of 24 1 10 1 10 100 1k 10k 100k 0 7642-035 frequency (hz) voltage noise density (nv/ hz) v sy = 15v figure 45. voltage noise density 1 10 100 1k 10k 100k 07642-045 frequency (hz) current noise density (pa/ hz) 0.1 1 10 correlated r s1 = r s2 uncorrelated r s1 = 0 ? v sy = 15v r s1 r s2 figure 46. current noise density input noise voltage (10nv/div) 07642-036 time (1s/div) v sy = 15v figure 47. 0.1 hz to 10 hz noise 1 10 1 10 100 1k 10k 100k 07642-038 frequency (hz) voltage noise density (nv/ hz) v sy = 5v figure 48. voltage noise density 1 10 100 1k 10k 100k 07642-046 frequency (hz) current noise density (pa/ hz) 0.1 1 10 correlated r s1 = r s2 uncorrelated r s1 = 0 ? v sy = 5v r s1 r s2 figure 49. current noise density input noise voltage (10nv/div) 07642-039 time (1s/div) v sy = 5v figure 50. 0.1 hz to 10 hz noise
ada4075-2 data sheet rev. b | page 14 of 24 2 4 6 8 4 6 8 1012141618 0 07642-048 supply voltage (v) supply current (ma) +125c +85c +25c ?40c figure 51. supply current vs. supply voltage v sy = 15v f = 1khz 600 ? 2k? 0.00001 0.0001 0.001 0.01 0.1 1 10 0.0001 0.001 0.01 0.1 1 10 07642-058 amplitude (v rms) thd + noise (%) figure 52. thd + noise vs. amplitude 100 1k 10k v sy = 15v v in = 3v rms 600? 2k? 0.0001 0.001 0.01 0.1 1 10 100k 07642-060 frequency (hz) thd + noise (%) figure 53. thd + noise vs. frequency 0 1 2 3 4 5 6 ?50 ?25 0 25 50 75 100 125 07642-057 temperature (c) supply current (ma) v sy = 15v v sy = 5v figure 54. supply current vs. temperature 0.00001 0.0001 0.001 0.01 0.1 1 10 0.0001 0.001 0.01 0.1 1 10 07642-065 amplitude (v rms) thd + noise (%) v sy = 5v f = 1khz 600 ? 2k ? figure 55. thd + noise vs. amplitude 0.0001 0.001 0.01 0.1 1 10 100 1k 10k 100k 07642-067 frequency (hz) thd + noise (%) v sy = 5v v in = 1.5v rms 600 ? 2k? figure 56. thd + noise vs. frequency
data sheet ada4075-2 rev. b | page 15 of 24 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 100 1k 10k 100k 07642-041 frequency (hz) channel separation (db) v sy = 15v v in = 10v p-p r l = 2k ? r l 100k ? 1k ? figure 57. channel separation vs. frequency v sy = 18v f = 1khz 600 ? 2k? 0.00001 0.0001 0.001 0.01 0.1 1 10 0.0001 0.001 0.01 0.1 1 10 100 07642-056 amplitude (v rms) thd + noise (%) figure 58. thd + noise vs. amplitude 0 0.5 1.0 1.5 2.0 2.5 ?50 ?25 0 25 50 75 100 125 07642-066 temperature (c) output voltage to supply rail (v) v+ ? v oh v ol ? v? v sy = 18v r l = 2k ? figure 59. output voltage to supply rail vs. temperature ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 100 1k 10k 100k 07642-044 frequency (hz) channel separation (db) v sy = 5v v in = 5v p-p r l = 2k ? r l 100k ? 1k? figure 60. channel separation vs. frequency 10 100 1k 10k 100k v sy = 18v v in = 8v rms 600? 2k? 0.00001 0.0001 0.001 0.01 0.1 1 07642-059 frequency (hz) thd + noise (%) figure 61. thd + noise vs. frequency 0.1 1 10 0.001 0.01 0.1 1 10 100 07642-068 load current (ma) output voltage to supply rail (v) v sy = 18v v+ ? v oh v ol ? v? figure 62. output voltage to supply rail vs. load current
ada4075-2 data sheet rev. b | page 16 of 24 applications information input protection to prevent base-emitter junction breakdown from occurring in the input stage of the ada4075-2 when a very large differential voltage is applied, the inputs are clamped by the internal diodes to 1.2 v. to preserve the ultralow voltage noise feature of the ada4075-2, the commonly used internal current-limiting resistors in series with the inputs are not used. in small signal applications, current limiting is not required; however, in applications where the differential voltage of the ada4075-2 exceeds 1.2 v, large currents may flow through these diodes. employ external current-limiting resistors as shown in figure 63 to reduce the input currents to less than 10 ma. note that depending on the value of these resistors, the total voltage noise will most likely be degraded. for example, a 1 k resistor at room temperature has a thermal noise of 4 nv/hz, whereas the ada4075-2 has an ultralow voltage noise of only 2.8 nv/hz typical. r2 r1 3 2 1 ada4075-2 07642-050 figure 63. input protection total harmonic distortion the total harmonic distortion + noise (thd + n) of the ada4075-2 is 0.0002% typical with a load resistance of 2 k. figure 64 shows the performance of the ada4075-2 driving a 2 k load with supply voltages of 4 v and 15 v. notice that there is more distortion for the supply voltage of 4 v than for a supply voltage of 15 v. therefore, it is important to operate the ada4075-2 at a supply voltage greater than 5 v for optimum distortion. the thd + noise graphs for supply voltages of 5 v and 18 v are available in figure 56 and figure 61 . 0.0001 0.001 0.01 0.1 1 10 100 1k 10k 100k 07642-069 frequency (hz) thd + noise (%) v sy = 4v r l = 2k ? v in = 1.5v rms v sy = 15v r l = 2k ? v in = 3v rms figure 64. thd + noise vs. frequency phase reversal an undesired phenomenon, phase reversal (also known as phase inversion) occurs in many op amps when one or both of the inputs are driven beyond the specified input common-mode voltage (v icm ) range, in effect reversing the polarity of the output. in some cases, phase reversal can induce lockups and cause equipment damage as well as self destruction. the ada4075-2 incorporates phase reversal prevention circuitry that clamps the output to 2 v typical from the supply rails when one or both inputs exceed the v icm range. figure 65 shows the input/output waveforms of the ada4075-2 configured as a unity- gain buffer for a supply voltage of 15 v. 07642-053 v in v out voltage (5v/div) time (40 s/div) v sy = 15v figure 65. no phase reversal
data sheet ada4075-2 rev. b | page 17 of 24 dac output filter the ultralow voltage noise, low distortion, and high slew rate of the ada4075-2 make it an ideal choice for professional audio signal processing. figure 66 shows the ada4075-2 used in a typical audio dac output filter configuration. the differential outputs of the dac are fed into the ada4075-2. the ada4075-2 is configured as a differential sallen-key filter. it operates as an external low-pass filter to remove high frequency noise present on the output pins of the dac. it also provides differential-to- single-ended conversion from the differential outputs of the dac. for a dac output filter, an op amp with reasonable slew rate and bandwidth is required. the ada4075-2 has a high slew rate of the 12 v/s and a relatively wide bandwidth of 6.5 mhz. the cutoff frequency of the low-pass filter is approximately 167 khz. in addition, the 100 k ? 47 f rc network provides ac coupling to block out the dc components at the output. 07642-054 output dac outn dac outp 11k ? 11k ? 5.62k ? 1.5k ? 3.01k ? 100 ? 5.62k ? 100k ? 2.2nf 150pf 270pf 560pf 68pf 47f ada4075-2 1/2 + figure 66. typical dac output filter circuit (differential)
ada4075-2 data sheet rev. b | page 18 of 24 balanced line driver the circuit of figure 67 shows a balanced line driver designed for audio use. such drivers are intended to mimic an output transformer in operation, whereby the common-mode voltage can be impressed by the load. furthermore, either output can be shorted to ground in single-ended applications without affecting the overall operation. circuits of this type use positive and negative feedback to obtain a high common-mode output impedance, and they are somewhat notorious for component sensitivity and susceptibility to latch-up. this circuit uses several techniques to avoid spurious behavior. first, the 4-op-amp arrangement ensures that the input impedance is load independent (the input impedance can become negative with some configurations). note that the output op amps are packaged with the input op amps to maximize drive capability. second, the positive feedback is ac-coupled by c2 and c3, which eliminates the need for offset trim. because the circuit is ac-coupled at the input, these capacitors do not have significant dc voltage across them, thus tantalum types of capacitors can be used. finally, even with these precautions, it is vital that the positive feedback be accurately controlled. this is partly achieved by using 1% resistors. in addition, the following setup procedure ensures that the positive feedback does not become excessive: 1. set r11 to its midposition (or short the ends together, whichever is easier) and temporarily short the negative output to ground. 2. apply a 10 v p-p sine wave at approximately 1 khz to the input and adjust r7 to provide 930 mv p-p at test (see figure 67 ). 3. remove the short from the negative output (and across r11, if used) and adjust r11 until the output waveforms are symmetric. the overall gain of the driver is equal to 2, which provides an extra 6 db of headroom in balanced differential mode. the output noise is about ?109 dbv in a 20 khz bandwidth. 07642-073 c3 10f r2 4.7k ? out+ out? 1/2 ada4075-2 r5 4.7k ? r6 4.7k ? r7 250? r8 100 ? r9 4.7k ? r13 100 ? r4 4.7k ? a2 1/2 ada4075-2 a1 in c5 50pf c1 10f c2 10f test symmetry trim feedback trim 1/2 ada4075-2 r12 4.7k ? r11 250 ? r17 4.7k ? r16 100 ? r10 4.7k ? r15 4.7k ? a4 c6 50pf 1/2 ada4075-2 a3 c4 50pf r14 100 ? r1 10k ? notes 1. all resistors should have 1% tolerance. 2. a1/a2 in same package; a3/a4 in same package. r3 4.7k ? r18 4.7k ? figure 67. balanced line driver
data sheet ada4075-2 rev. b | page 19 of 24 balanced line receiver figure 68 depicts a unity-gain balanced line receiver capable of a high degree of hum rejection. the cmrr is approximately given by ? ? ? ? ? ? ? ? ? ? r3r2 r4r1 10 log20 therefore, r1 to r4 should be close tolerance components to obtain the best possible cmrr without adjustment. the presence of a2 ensures that the impedances are symmetric at the two inputs (unlike many other designs), and, as a bonus, a2 also provides a complementary output. a3 raises the common-mode input impedance from approximately 7.5 k to approximately 70 k, reducing the degradation of cmrr due to mismatches in source impedance. note that a3 is not in the signal path, and almost any op amp works well here. although it may seem as though the inverting output should be noisier than the noninverting one, they are in fact symmetric at about ?111 dbv (20 khz bandwidth). sometimes an overall gain of ? is desired to provide an extra 6 db of differential input headroom. this can be attained by reducing r3 and r4 to 5 k and increasing r9 to 22 k. r5 5k ? out? out+ in? *a3 reduces the degradation of cmrr (see the balanced line receiver section for more details). c1 22f (non-polar) in+ 07642-071 r4 10k ? 1/2 ada4075-2 r3 10k ? r6 5k ? r1 5k ? r2 5k ? c2 50pf r9 11k ? a3* r8 5.6k ? r7 5.6k ? 1/2 a1 a2 ada4075-2 c3 50pf r10 11k ? figure 68. balanced line receiver
ada4075-2 data sheet rev. b | page 20 of 24 low noise parametric equalizer the circuit in figure 69 is a reciprocal parametric equalizer yielding 20 db of cut or boost with variable bandwidth and frequency. the frequency control range is 6.9:1, with the geometric mean center frequency conveniently occurring at the midpoint of the potentiometer setting. the center frequency is equal to 48 hz/ct, where ct is the value of c1 and c2 in microfarads. the bandwidth control adjusts the q from 0.9 to about 11. the overall noise is setting dependent, but with all controls centered, it is about ?104 dbv in a 20 khz bandwidth. such a low noise level can obviate the need for a bypass switch in many applications. 07642-074 1/2 c2* 100 ? 1k ? bandwidth *the center frequency is affected by the value of c1 and c2 (see the low noise parametric equalizer section for more details). 1.3k ? 1/2 1/2 c1* 2.5k ? 620 ? 2.5k ? 620 ? 1.5k ? 1.3k ? 2.5k ? 1/2 ada4075-2 ada4075-2 ada4075-2 ada4075-2 6.2k ? 6.2k ? 47f 5k ? boost cut 1.5k ? in out 2.5k ? 2.7k ? 620 ? frequency (ganged potentiometer) figure 69. low noise parametric equalizer
data sheet ada4075-2 rev. b | page 21 of 24 schematic 07642-072 ?ina/ ?inb +ina/ +inb outa/ outb v + v? figure 70. simplified schematic
ada4075-2 data sheet rev. b | page 22 of 24 outline dimensions controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design. compliant to jedec standards ms-012-a a 012407-a 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) 0.50 (0.0196) 0.25 (0.0099) 45 8 0 1.75 (0.0688) 1.35 (0.0532) seating plane 0.25 (0.0098) 0.10 (0.0040) 4 1 85 5.00 (0.1968) 4.80 (0.1890) 4.00 (0.1574) 3.80 (0.1497) 1.27 (0.0500) bsc 6.20 (0.2441) 5.80 (0.2284) 0.51 (0.0201) 0.31 (0.0122) coplanarity 0.10 figure 71. 8-lead standard small outline package [soic_n] narrow body (r-8) dimensions shown in millimeters and (inches) 051608-a top view 8 1 5 4 0.30 0.25 0.18 bottom view pin 1 index area 2.00 bsc sq seating plane 0.60 0.55 0.50 0.20 ref 0.05 max 0.02 nom 0.65 0.60 0.55 0.50 bsc p i n 1 i n d i c a t o r figure 72. 8-lead lead frame chip scale package [lfcsp_wd] 2 mm 2 mm body, very very thin, dual lead (cp-8-6) dimensions shown in millimeters ordering guide model 1 temperature range package description package option branding ada4075-2arz ?40c to +125c 8-lead soic_n r-8 ada4075-2arz-r7 ?40c to +125c 8-lead soic_n r-8 ada4075-2arz-rl ?40c to +125c 8-lead soic_n r-8 ada4075-2acpz-r7 ?40c to +125c 8-lead lfcsp_wd cp-8-6 a0 ada4075-2acpz-rl ?40c to +125c 8-lead lfcsp_wd cp-8-6 a0 1 z = rohs compliant part.
data sheet ada4075-2 rev. b | page 23 of 24 notes
ada4075-2 data sheet rev. b | page 24 of 24 notes ?2008C2011 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d07642-0-12 /11(b)

▲Up To Search▲

Price & Availability of AD8671

	To Download AD8671 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .